In a modern wireline high-speed digital communication system, data is transmitted at a very high rate. A typical high-speed digital link may send the binary data at 25 Giga bit per second (Gbps) or higher. In a 25 Gbps link for example, information in the form of 0 and 1 (bits) are sent at a speed of 1 bit per 40 picoseconds. In this example, 40 picoseconds is the time interval, also called bit-width or unit interval (UI), over which one bit of information is transmitted. The signal at the receiver is distorted by the bandwidth limited channel (channel loss) causing inter-symbol interference (ISI), jitter or the uncertainty in the exact timing of the transmitter clock edges resulting in uncertainty in exact timing of the transmitted data, crosstalk such as interference by adjacent links, and noise.
To recover the transmitted data with low error probability, the received distorted analog signal is equalized and sampled according to a clock signal recovered from the received signal using a clock and data recovery (CDR) circuit. A commonly used technique to remove the ISI without amplifying the noise and crosstalk is called decision feedback equalization (DFE.) A detailed description of the decision-feedback equalizers, can be found in, for example J. R. Barry, E. A. Lee and D. G. Messerschmitt, Digital Communication, vol. I, Springer Science & Business Media, LLC, 2004. A DFE circuit receives data retrieved by slicer. The DFE circuit removes the ISI from the signal prior to sampling by continuously generating the same ISI caused by previously recovered data and subtracting the generated ISI from the received signal. However, successful recovery of the transmitted data using DFE is strongly dependent on optimal and adaptive adjustment of the sampling clock signal in the CDR. As such, the sampling clock phase must be accurate and with minimum uncertainty and jitter.